Inside a today's typical VLSI system, there are millions of electrical signals. They make the system perform what it is designed to do. Among those, the most important one is the clock signal. From an operational perspective, clock is the timekeeper of the electrical world inside the chip. From a structural perspective, clock generator is the heart of the chip; clock signal is the blood; and clock distribution network is the vessel.
Timekeeper has played and is playing a critical role in our human life. History shows that the progressive advancement of our civilization is only made possible by the steady refinement of the timekeeper: the clock/watch. The same is true for VLSI system. The purpose of VLSI system is for processing information. The efficiency of performing this task is highly dependent on the time scale used. This time scale is controlled by the clock signal. It has two key aspects: its size (the absolute clock frequency) and its resolution (the capability of differentiating nearby frequencies). In addition, another characteristic is also important: the speed that time scale can be switched from one to another (the speed of clock frequency switching). Phase Locked Loop (PLL) has traditionally been used as on-chip generator of clock signal. It is a beautiful blend of digital and analog circuits in one piece of hardware. From a reference time scale, it can generate other time scales. However, due to its usage of compare-then-correct feedback mechanism, the choice of time scales that can be produced is limited. Equally serious is the problem that the change of time scale (frequency switching in PLL) takes very long time. Although PLL has played a key role that makes today's VLSI system magnificent, these two problems are limiting chip architect's capability for creating further innovation.
The source of the problem originates from the very fact that electrical circuit is not born for handling time, but magnitude (or level). Inside a circuit, information is represented by the medium of electron. It is created on the magnitude of electron flow, using proportional (analog) or binary (digital) relationships. Time is created indirectly through a voltage level crossing a predetermined threshold. Therefore, the task of building a timekeeper inside VLSI system is inherently difficult. In implementation, another fact has made the task of creating time inside circuit even more challenging: since the first day that clock signal is introduced into VLSI design, it is assumed that all the pulses inside a particular clock pulse train have to be equal-in-length. This presupposition has limited our options in the creation of timekeeper circuit. Consequently, our current solution is not completely satisfactory: 1) we cannot generate any arbitrary clock frequency we want. 2) we cannot switch the frequency of clock signal quickly.
Since timekeeper controls VLSI system's operation pace through clock-driving-circuit, a fundamental question can be asked: do all the pulses in a clock pulse train have to be equal-in-length? This question is equivalent to asking: what does clock frequency really mean? In 2008 a novel concept, Time-Average-Frequency, is introduced [1]. It removes the constraint that all pulses (or clock cycles) must be equal-in-length. It is based on the understanding that clock frequency is used to indicate the number of operations executed (or events happened) within the time window of one second. As long as the specified number of operations is completed successfully in a specified time window (such as one billion operations within one second for a 1 GHz CPU), the system does not care how each operation is carried out in detail.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.